wiki:Reparaturanleitung

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Instructions for repair and fault-finding

General problems putting the SDR in operation with Windows

Try Bonito RadioJet RJ10FiFi. The installation process is very simple. You only need the driver, which is available here.

Frequecy offset

  • Offset is increasing with the LO frequency: Your si570 oscillator is not calibrated. Self-calibration is possible.
  • Constant 12 kHz offset: This occurs depending on your SDR software. HDSDR for example should always be correct. For other tools, an individual offset can be adjusted.
  • In both cases, see the wiki page Frequency calibration for assistance.

Other software or firmware related problems

Please first install rockprog. This enables all data necessary for analysis to be gathered. The Easy operation mode provides a menu item "Perform Diagnosis", generating a text file named diag.txt. When the file has been created, simply click on "New Ticket", describe your problem as accurately as possible and add the diag.txt file as an attachment. We will try to help you with your problem!

Bad reception, sensivity is not OK

  • Most common cause: Insufficient soldering at the BNC connector or the pin row to the preselector (especially GND pins)
  • Preamp defective (check operating points, see below)
  • Protection diode defective (try without)
  • other soldering or component troubles (create new ticket)

Noise peaks with 1 kHz distance

This noise is caused by the USB bus. This Frequency is generated in the computer, not in the SDR. Try to use a high quality USB cable.


Hardware Problems with home-made FiFi-SDR

These instructions were intended for the early revisions 1.0 and 1.1, which have been given away by the OV Lennestadt as assembly kits. It can also be helpful for repairing the FUNKAMATEUR Edition (Rev 1.2 and later).

Visual inspection before putting into operation

  • Have the ICs and the Si570 oscillator been installed the correct way round?
  • Are IC3 and IC8 swapped (the two 16-leg devices)? IC3 is from NXP and IC8 normally from TI. Bild von IC3 und IC8 von DF7DJ
  • Have the tantalum caps been installed as printed (only exception is C58 up to Rev 1.1)?
  • Solder blobs (esp. on Si570, see below)

Function LED

  • The LED must start to blink when the USB cable is plugged in. If it doesn't, either the microcontroller has not been correctly flashed or there is a different hardware problem near the microcontroller.
  • If after flashing, the LED first stays on constantly for around 10 seconds and only then starts to blink, there is probably a ground connection of the SCL signal. The short circuit is probably directly on the Si570 as the area beside Pin 8 that is kept free by the solder resisting paint is too large so that part of the ground area is without paint (see diagram). The problem occurs frequently with Rev 1.1 and has been resolved as from Rev 1.3.
    SCL-Masseschluss am si570

Supply voltages

  • Three test points are provided for the output of the voltage regulator. They are Vias that are marked on the board with "+3V3" (TOP layer, upper middle), "+3V3_SWI" (TOP layer, at the top near the oscillator) and "+4V_SWI" (TOP layer, bottom right). These voltages must all be present.
  • There must also be an auxiliary voltage of c. 1.65 Volts measured on pin 3 or 5 of the OP (IC5).
  • A common problem is either an unsoldered heatsink of NCP5500 (IC7) or a cold joint. Please use a lot of heat here! Indications of this fault are:
    • the +3V3_SWI voltage is missing
    • the radio is sensitive to being touched or jolted
    • the current consumption is far too low (c. 80 mA instead of 170 mA)
    • EN pin of the NCP5500 has c. 2.3 V instead of 3.3 V

Analog section

The values given in this part were measured with a 1 MHz signal at 1 mV (- 47 dBm) fed to the BNC socket.

Measurement points in the analog section

Rev 1.0:

  • Gate T3: ca. 1.4 - 1.6 Volt
  • Drain T3: 3.5 Volt
  • Source T3 = Base T2: c. 1.6 - 1.8 Volt
  • Collector T2: 3.6 Volt
  • Emitter T2: 0.95 Volt
  • Basis T5: 1.45 Volt
  • Collector T5: 3.7 Volt
  • Emitter T5: 0.7 Volt

Rev 1.1 and Rev 1.2 (first FA edition until mid 2011):

  • Gate T3: ca. 1.4 - 1,6 Volt
  • Drain T3: 3.5 Volt
  • Source T3 = Base T2: c. 1.6 - 1.8 Volt
  • Collector T2: 2.6 Volt
  • Emitter T2: 1.0 Volt
  • Basis T5: 1.9 Volt
  • Collector T5: 3.35 Volt
  • Emitter T5: 1.15 Volt

Rev 1.2 (second FA edition as from October 2011), Rev 1.3 (internal):

  • Gate T3: ca. 1.4 - 1.6 Volt
  • Drain T3: 3.5 Volt
  • Source T3 = Base T2: c. 1.6 - 1.8 Volt
  • Collector T2: 2.8 Volt
  • Emitter T2: 0.9 Volt
  • Basis T5: 1.5 Volt
  • Collector T5: 3.2 Volt
  • Emitter T5: 0.7 Volt

If the voltage on the gate of FET T3 is significantly higher than given here and no error has been made in fitting the components then the FET is probably defective.

Known placement errors

  • T5: Base 1.0 Volt and collector 0.2 Volt: R43: 4k7 has been fitted instead of 4R7
  • T5: Collector near 4 Volt: R5 or R26 not correctly soldered.

Signal forms in the analog section

The reference ground point for the oscilloscope is to be made bottom right on the area held free by solder resisting paint. A short wire can also be attached easily here. The frame of the button is not at ground potential and can therefore not be used.

All the screenshots in the following section were taken with a 1:1 probe. If a 1:10 probe is being used, the level may have to be raised (e.g. up to -27 dBm) to enable the oscilloscope to display the signals.

The SDR software must be started on the PC and a frequency of 1 MHz selected.

  • Output of the transformer (Pin 3, lower left): a higher level can be seen due to the impedance transformation, c. 11.5 mVss.
    Ausgang des Trafos
    Note: the signal shown has 1 MHz and not 43 kHz as shown in the picture.
  • The same signal must also appear on the gate of T3 (slightly lower level, in the region of a few hundred nVss)
  • Collector of T2: the signal must be larger than c. 20 mV, then the preamp is working correctly.
    Collector T2
  • The same signal must also appear on the base of T5 (slightly lower level, just a few mV)
  • Now two channels are needed. Channel 1 shows the collector of T5, channel 2 the emitter of T5. The signal must be 180° phase reversed and at the same level. Here we can see oscillator disturbance (1 MHz divided by 4 equals the 250 ns peaks).
    1: Collectort T5, 2: Emitter T5
  • The same signal must also appear on DIFF_A and DIFF_B. If the levels are not the same here then there is probably the wrong resistor fitted, e.g. R26 at 56k instead of 56R.

The following section describes the checks of the input signals of the mixer. It can be left out if the output signals are correct

  • Channel 1: Signal 1OE (IC8 Pin 2), Channel 2: Signal 2OE (IC8 Pin 5): 180° phase shift
    1: 1OE (Switch Pin 2), 2: 2OE (Switch Pin 5)
  • Channel 1: Signal 1OE (IC8 Pin 2), Channel 2: Signal 3OE (IC8 Pin 12): 90° phase shift
    1: 1OE (Switch Pin 2), 2: 3OE (Switch Pin 12)
  • Channel 1: Signal 1OE (IC8 Pin 2), Channel 2: Signal 4OE (IC8 Pin 15): 90° phase shift
    1: 1OE (Switch Pin 2), 2: 4OE (Switch Pin 15)

Now measurements are taken after the mixer. For this, a 10 kHz shift is set in the SDR software on the PC i.e. a frequency of 1010 kHz.

  • Channel 1: Plus pin of C26, Channel 2: Plus pin of C27: The signal must be shifted 90° (not 180°!) and be close to the same level.
    1: C26, 2: C27
  • Channel 1: Pin 1 of the OP (IC5), Channel 2: Pin 7 of the OP (IC5). If the levels are not identical please check R21 and R24.
    1: OP Pin 1, 2: OP Pin 7

Signal forms at the codec IC

If the integrated sound card is not functioning, this is often because the signal from the microcontroller is missing.

  • Pin 13: Signal DATAO: output of digital data stream. When this signal is preset everything is OK. If not, please check for the signals below.
    ADC Pin 13
  • 3.3 Volt on Pin 9 and Pin 16 present? Ground pins 6, 7 and 15 OK?
  • LF input signals on Pins 1 (R39) and 3 (R40) present?
  • Pin 8: 24 MHz "teeth" from the µC:
    Pin 8 IC9
  • Pin 12: Signal WS (word select): 96 kHz tooth. If the signal is missing there will be nothing to measure on Pin 11.
    ADC Pin 12
  • Pin 11: Signal BCK (bit clock): A tooth here too but at c. 6.15 MHz
    ADC Pin 11

Logic levels of the divider signals

  • The three control signals TEILER1, TEILER2 and TEILER3 are driven differently by the CPU depending on the reception frequency. The switching points of TEILER1 and TEILER2 are permanently programmed:
    1. 0 < f < 200 kHz: TEILER1=0, TEILER2=0
    2. 200 kHz <= f < 800 kHz: TEILER1=1, TEILER2=0
    3. 800 kHz <= f < 2.5 MHz: TEILER1=0, TEILER2=1
    4. 2.5 MHz <= f < inf: TEILER1=1, TEILER2=1
  • It is always TEILER3=1 if the set frequency lies above the switching point for reception on the 3rd harmonic, but still under the frequency for reception on the 5th harmonic. Outside this range TEILER3=0.

Further help

Was there no applicable help on this page for your problem? Then simply click on "New Ticket" and describe your problem as accurately as possible. We will try to help you with your problem!

Last modified 4 years ago Last modified on Jan 21, 2013 10:08:34 PM

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